MD1213 features 6ns rise and fall time with 1000pf load 2.0a peak output source/sink current 1.2v to 5v input cmos compatible 4.5v to 13v total supply voltage smart logic threshold low jitter design two matched channels outputs can swing below ground low inductance package thermally-enhanced package applications medical ultrasound imaging piezoelectric transducer drivers nondestructive evaluation pin diode driver ccd clock driver/buffer high speed level translator ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? general description the supertex MD1213 is a high speed, dual mosfet driver. it is designed to drive high voltage p and n-channel mosfet transistors for medical ultrasound and other applications requiring a high output current for a capacitive load. the high-speed input stage of the MD1213 can operate from 1.2v to 5.0v logic interface with an optimum operating input signal range of 1.8v to 3.3v. an adaptive threshold circuit is used to set the level translator switch threshold to the average of the input logic 0 and logic 1 levels. the input logic levels may be ground referenced, even though the driver is putting out bipolar signals. the level translator uses a proprietary circuit, which provides dc coupling together with high-speed operation. the output stage of the MD1213 has separate power connections enabling the output signal l and h levels to be chosen independently from the supply voltages used for the majority of the circuit. as an example, the input logic levels may be 0 and 1.8volts, the control logic may be powered by +5.0v and C5.0v, and the output l and h levels may be varied anywhere over the range of C5.0v to +5.0v. the output stage is capable of peak currents of up to 2.0a, depending on the supply voltages used and load capacitance present. the oe pin serves a dual purpose. first, its logic h level is used to compute the threshold voltage level for the channel input level translators. secondly, when oe is low, the outputs are disabled, with the a output high and the b output low. this assists in properly pre- charging the ac coupling capacitors that may be used in series in the gate drive circuit of an external pmos and nmos transistor pair. typical application circuit high speed dual mosfet driver v dd 2 v h v l in a out a in b level shifter oe v ss 2 v l out b v ss 2 level shifter level shifter v dd 2 v h v ss 1 gnd v dd 1 supertex tc6320 1f +100v 1f -100v to piezoelectric transducer 10nf 10nf 0.47f +5v MD1213 3.3v cmos logic inputs 0.47f -5v
2 MD1213 ordering information device package option 12-lead 4x4x0.8pitch qfn MD1213 MD1213k6-g absolute maximum ratings parameter value v dd -v ss , logic supply voltage -0.5v to +13.5v v h , output high supply voltage v l - 0.5v to v dd +0.5v v l , output low supply voltage v ss - 0.5v to v h +0.5v v ss , low side supply voltage -7.0v to +0.5v logic input levels v ss -0.5v to v ss +7.0v maximum junction temperature +125c storage temperature -65c to 150c operating temperature -20c to 85c -g indicates package is rohs compliant (green) absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. pin con? guration 1 7 12 10 4 9 6 3 12-lead qfn (k6) (top view) dc electrical characteristics (over operating conditions unless otherwise speci? ed, v h = v dd1 = v dd2 = 12v, v l = v ss1 = v ss2 = 0v, v oe = 3.3v, t j = 25c) sym parameter min typ max units conditions v dd - v ss logic supply voltage 4.5 - 13 v --- v ss logic side supply voltage -5.5 - 0 v --- v h output high supply voltage v ss + 2.0 - v dd v --- v l output low supply voltage v ss -v dd - 2.0 v --- i dd1q v dd1 quiescent current - 0.55 - ma no input transitions i dd2q v dd2 quiescent current - - 10 a i hq v h quiescent current - - 10 a i dd1 v dd1 average current - 0.88 - ma one channel on at 5.0mhz, no load i dd2 v dd2 average current - 6.6 - ma i h v h average current - 23 - ma v ih input logic voltage high v oe - 0.3 - 5.0 v for logic inputs in a and in b v il input logic voltage low 0 - 0.3 v i ih input logic current high - - 1.0 a i il input logic current low - - 1.0 a package marking 1213 ywll y = last digit of year sealed w = code for week sealed l = lot number = green packaging 12-lead qfn (k6)
3 MD1213 logic truth table outputs (v h = v dd1 = v dd2 = 12v, v l = v ss1 = v ss2 = 0v, v oe = 3.3v, t j = 25c) sym parameter min typ max units conditions v ih oe input logic voltage high 1.2 - 5.0 v for logic input oe v il oe input logic voltage low 0 - 0.3 v r in input logic impedance to gnd 12 20 30 k c in logic input capacitance - 5.0 10 pf all inputs ja thermal resistance to air - 47 - c/w 1oz. 4-layer 3x4 pcb with thermal pad and thermal via array jc thermal resistance to case - 7.0 - c/w --- r sink output sink resistance - - 12.5 i sink = 50ma r source output source resistance - - 12.5 i source = 50ma i sink peak output sink current - 2.0 - a --- i source peak output source current - 2.0 - a --- ac electrical characteristics (v h = v dd1 = v dd2 = 12v, v l = v ss1 = v ss2 = 0v, v oe = 3.3v, t j = 25c) sym parameter min typ max units conditions t irf inputs or oe rise & fall time - - 10 ns logic input edge speed requirement t plh propagation delay when out- put is from low to high - 7.0 - ns c load = 1000pf, see timing diagram input signal rise/fall time of 2ns t phl propagation delay when out- put is from high to low - 7.0 - ns t poe propagation delay oe to outputs - 9.0 - ns t r output rise time - 6.0 - ns t f output fall time - 6.0 - ns l t r - t f l rise and fall time matching - 1.0 - ns for each channel l t plh -t phl l propagation low to high and high to low matching - 1.0 - ns t dm propagation delay match - 2.0 - ns device to device delay match logic inputs output oe in a in b out a out b hllv h v h hlhv h v l hh lv l v h hhhv l v l lxxv h v l
4 MD1213 propagation delay logic input threshold 1 1.5 2 2.5 3 3.5 6.0 7.0 8.0 9.0 10 propagation delay vs. logic voltage logic voltage (v) propagation delay (ns) 0 0.5 1.0 1.5 2.0 v th vs. v oe 1.0 2.0 3.0 4.0 5.0 v oe (volts) v th (volts) v oe /2 0.6v detailed block diagram v dd2 v h v l in a out a in b level shifter oe v ss2 v l out b v ss2 level shifter level shifter v dd2 v h v ss1 gnd v dd1 sub
5 MD1213 in t plh 10% 9 0 % 5 0 % 5 0 % out t phl t r 90% 10% t f 3.3v 0v 0v timing diagram simpli? ed block diagram v l v ss2 v ss1 gnd out a out b v dd2 v h in a in b oe v dd1 MD1213 v dd 2 v h v l in a out a in b level shifter oe v ss 2 v l out b v ss 2 level shifter level shifter v dd 2 v h v ss 1 gnd v dd 1 supertex tc6320 1f +100v 1f -100v to piezoelectric transducer 10nf 10nf 0.47f +12v MD1213 3.3v cmos logic inputs single supply application circuit
6 MD1213 application information for proper operation of the MD1213, low inductance bypass capacitors should be used on the various supply pins. the gnd input pin should be connected to the digital ground. the ina, inb, and oe pins should be connected to their logic source with a swing of gnd to logic level high, which is 1.2v to 5.0v. good trace practices should be followed corre- sponding to the desired operating speed. the internal circuit- ry of the MD1213 is capable of operating up to 100mhz, with the primary speed limitation being the loading effects of the load capacitance. because of this speed and the high tran- sient currents that result with capacitive loads, the bypass capacitors should be as close to the chip pins as possible. unless the load speci? cally requires bipolar drive, the v ss1 , v ss2 , and v l pins should have low inductance feed-through connections directly to a ground plane. if these voltages are not zero, then they need bypass capacitors in a manner sim- ilar to the positive power supplies. the power connections v dd1 and v dd2 should have a ceramic bypass capacitor to the ground plane with short leads and decoupling components to prevent resonance in the power leads. a common capacitor and voltage source may be used for these two pins, which should always have the same dc voltage applied. for ap- plications sensitive to jitter and noise, separate decoupling networks may be used for v dd1 and v dd2 . the supplied voltages of v h and v l determine the output logic levels. these two pins can draw fast transient currents of up to 2.0a, so they should be provided with an appropri- ate bypass capacitor located next to the chip pins. a ceramic capacitor of up to 1.0f may be appropriate, with a series ferrite bead to prevent resonance in the power supply lead coming to the capacitor. pay particular attention to minimiz- ing trace lengths and using suf? cient trace width to reduce inductance. surface mount components are highly recom- mended. since the output impedance of this driver is very low, in some cases it may be desirable to add a small series resistor in series with the output signal to obtain better wave- form integrity at the load terminals. this will of course reduce the output voltage slew rate at the terminals of a capacitive load. pay particular attention to the parasitic coupling from the driver output to the input signal terminals. this feedback may cause oscillations or spurious waveform shapes on the edges of signal transi- tions. since the input operates with signals down to 1.2v, even small coupled voltages may cause problems. use of a solid ground plane and good power and signal layout prac- tices will prevent this problem. be careful that the circulating ground return current from a capacitive load cannot react with common inductance to cause noise voltages in the in- put logic circuitry. pin description pin # name description 1in a logic input. controls out a when oe is high. input logic high will cause the output to swing to v l . input logic low will cause the output to swing to v h . 2v l supply voltage for n-channel output stage. 3in b logic input. controls out b when oe is high. input logic high will cause the output to swing to v l . input logic low will cause the output to swing to v h . 4 gnd logic input ground reference. 5v ss1 low side analog circuit and level shifter supply voltage. should be at the same potential as v ss2 . 6v ss2 low side gate drive supply voltage. 7out b output driver. swings from v h to v l . intended to drive the gate of an external n-channel mosfet via a series capacitor. when oe is low, the output is disabled. out b will swing to v l turning off the external n-channel mosfet. 8v h supply voltage for p-channel output stage. 9out a output driver. swings from v h to v l . intended to drive the gate of an external p-channel mosfet via a series capacitor. when oe is low, the output is disabled. out a will swing to v h turning off the external p-channel mosfet. 10 v dd2 high side gate drive supply voltage. 11 v dd1 high side analog circuit and level shifter supply voltage. should be at the same potential as v dd2 . 12 oe output-enable logic input. when oe is high, (v oe + v gnd )/2 sets the threshold transition between logic level high and low for in a and in b . when oe is low, out a is at v h and out b is at v l regardless of in a and in b note: 1.thermal pad and pin#5 (v ss1 ) must be connected externally. 2. index pad and thermal pad are connected internally
7 MD1213 (the package drawing(s) in this data sheet may not re? ect the most current speci? cations. for the latest package outline information go to http://www.supertex.com/packaging.html .) 12-lead qfn package outline (k6) 4x4mm body, 1.0mm height (max), 0.80mm pitch symbol a a1 a3 b d d2 e e2 e l l1 dimension (mm) min 0.80 0.00 0.20 ref 0.20 4.00 bsc 2.00 4.00 bsc 2.00 0.80 bsc 0.30 0.03 0 o nom 0.90 0.02 0.30 2.15 2.15 - - - max 1.00 0.05 0.35 2.25 2.25 0.50 0.15 14 o drawings not to scale. notes: details of pin 1 identi? er are optional, but must be located within the indicated area. the pin 1 identi? er may be either a m old, or an embedded metal or marked feature. depending on the method of manufacturing, a maximum of 0.15mm pullback (l1) may be present. the inner tip of the lead may be either rounded or square. 1. 2. 3. seating plane top view side view bottom view a a1 d e d2 e b e2 a3 l l1 view b view b 1 12 note 3 note 2 note 1 (index area d/2 x e/2) note 1 (index area d/2 x e/2) 1 12 doc.# dsfp-MD1213 nr072007
|
